Fourteen Angstroms
A silicon atom is roughly 2 angstroms in diameter. Fujitsu is building transistors at 14 angstroms -- 1.4 nanometers -- for a neural processing unit optimized specifically for AI inference. To put that in perspective, the width of a DNA double helix is about 2 nanometers. We're talking about transistor gates smaller than the molecule that encodes life.
This isn't a research paper or a conference demo. Fujitsu is developing this chip for production at Rapidus, a semiconductor fabrication company operating out of a facility in Hokkaido, Japan. The funding is real, the timeline is aggressive, and the implications for the global chip supply chain are significant.
The Rapidus Bet
Rapidus is arguably the most ambitious semiconductor venture in the world right now, and most developers have never heard of it. The company secured $1.7 billion in funding from a combination of Japanese government support and 32 private companies. The investor list reads like a who's who of Japanese industry: Canon, Fujitsu, NTT, SoftBank, Sony, among others.
Here's what makes Rapidus remarkable: Japan's most advanced domestic chip manufacturing has been at the 40nm node. Rapidus is attempting to jump directly to 2nm, skipping 28nm, 14nm, 10nm, 7nm, 5nm, and 3nm entirely. That's like a car manufacturer going from building horse carriages to electric hypercars with nothing in between.
The 2nm mass production target is H2 2027. They've already released their first 2nm process design kit (PDK) to early-access customers, and they report having 60+ prospective customers spanning AI, robotics, and edge computing. The 1.4nm production -- the Fujitsu AI chip -- is planned for around 2029.
Why 1.4nm Matters for AI Inference
There's an important distinction between training and inference in AI workloads, and it directly explains why this chip matters.
Training a large model requires massive parallel computation -- the kind of workload that NVIDIA's H100 and B200 GPUs dominate. But inference -- actually running a trained model to generate predictions -- has different characteristics. It's more about throughput, latency, and power efficiency than raw floating-point performance.
# The inference optimization problem, simplified
# Training: maximize FLOPS, power budget is secondary
# Inference: minimize latency per token while maximizing tokens per watt
class InferenceChipMetrics:
def __init__(self, process_node_nm, tdp_watts, tokens_per_second):
self.process_node = process_node_nm
self.tdp = tdp_watts
self.throughput = tokens_per_second
@property
def efficiency(self):
"""Tokens per watt -- the metric that matters for inference at scale"""
return self.throughput / self.tdp
@property
def cost_per_million_tokens(self, electricity_cost_kwh=0.10):
"""Operational cost drives inference economics"""
watts_per_token = self.tdp / self.throughput
kwh_per_million = (watts_per_token * 1_000_000) / (3600 * 1000)
return kwh_per_million * electricity_cost_kwh
# Hypothetical comparison (illustrative, not benchmarked)
current_gen = InferenceChipMetrics(process_node_nm=4, tdp_watts=300, tokens_per_second=5000)
fujitsu_npu = InferenceChipMetrics(process_node_nm=1.4, tdp_watts=150, tokens_per_second=12000)
# Smaller process = less power per transistor switching
# Purpose-built NPU = optimized datapath for transformer ops
# Result: dramatically better tokens-per-watt
Fujitsu's 1.4nm NPU is designed specifically for this inference workload. By building a purpose-built chip at an extremely advanced process node, they're targeting the efficiency frontier -- more inference throughput per watt of power consumed. At data center scale, this translates directly to cost per token served.
The Global Chip Supply Chain Implications
Right now, the advanced semiconductor manufacturing landscape is dominated by TSMC in Taiwan and Samsung in South Korea. Intel is attempting a comeback with its foundry services. That's essentially it for cutting-edge logic chips.
Adding Japan as a serious player at the 2nm node (and eventually 1.4nm) changes the geopolitical calculus around chip supply. Taiwan's dominance in advanced manufacturing has been a source of strategic anxiety for essentially every major economy. A functional Japanese alternative, even at smaller scale, provides a diversification option that didn't previously exist.
For developers, this matters more than you might think. The cost and availability of inference compute directly affects the economics of every AI-powered application:
# How fab diversity affects your inference costs over time
import dataclasses
from typing import List
@dataclasses.dataclass
class FabCapacity:
name: str
region: str
min_node_nm: float
monthly_wafer_capacity: int
ai_chip_allocation_pct: float
# 2027-2029 projected advanced node landscape
fabs: List[FabCapacity] = [
FabCapacity("TSMC Fab 20", "Taiwan", 2.0, 50_000, 0.35),
FabCapacity("Samsung Pyeongtaek", "South Korea", 2.0, 30_000, 0.25),
FabCapacity("Intel 18A", "US/Ireland", 1.8, 20_000, 0.20),
FabCapacity("Rapidus Hokkaido", "Japan", 2.0, 10_000, 0.60),
# By 2029: Rapidus 1.4nm line for Fujitsu NPU
]
total_ai_wafers = sum(f.monthly_wafer_capacity * f.ai_chip_allocation_pct for f in fabs)
rapidus_share = (10_000 * 0.60) / total_ai_wafers
# Even at modest capacity, Rapidus adds meaningful supply
# More supply = more competition = lower inference costs
# Lower inference costs = more viable AI applications
The numbers above are illustrative, but the dynamic is real. Every new source of advanced chip manufacturing puts downward pressure on inference costs. And inference costs are the single biggest variable cost for most AI-powered software.
The Fugaku Connection
There's another dimension to Fujitsu's 1.4nm chip that's easy to overlook. The chip is being integrated with a CPU for Fugaku NEXT, the successor to Japan's Fugaku supercomputer. Fugaku held the top spot on the TOP500 list from 2020 to 2022 and remains one of the most powerful systems in the world.
Fugaku NEXT with purpose-built AI inference silicon represents a different approach to supercomputing -- one that treats AI workloads as a first-class concern rather than bolting GPU accelerators onto a traditional architecture. This is the kind of system that could run massive inference workloads for an entire research ecosystem.
What Developers Should Watch
The 2029 timeline for 1.4nm production might seem distant, but the intermediate milestones matter now. Rapidus's 2nm mass production in H2 2027 is the proving ground. If they hit that target, the 1.4nm roadmap becomes credible in a way it isn't today.
For developers building AI-powered applications, the practical takeaway is this: inference costs are going to fall, probably faster than most projections assume. More fabs, more competition, more purpose-built silicon all point in the same direction. Applications that are marginally uneconomical today because of inference costs may become viable within 2-3 years purely from hardware improvements.
The fact that Japan is making this leap -- from 40nm to 2nm, with 1.4nm in sight -- is a reminder that the semiconductor industry doesn't follow a single linear path. Sometimes a country decides to skip the incremental steps and bet everything on a generational jump. Whether Rapidus pulls it off will be one of the most consequential industrial stories of the decade.
If you're making architectural decisions today about how tightly to couple your application to specific hardware or cloud providers, it's worth remembering that the inference compute landscape in 2029 will look nothing like it does now. Design for flexibility. The chips are coming.
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